Storing a bit: charge, magnetism and light

To store a bit, you need a physical system with at least two states that are easy to tell apart, stay put when left alone, and can be changed on demand. "Stay put" is the hard part. Every state is being shaken by heat, with a typical energy of kT = 25.9 meV at room temperature, as the first chapter computed. A bit lasts as long as the barrier between its two states stays high compared with kT — or as long as something keeps restoring it.

Computers use four families of answers: a feedback loop that restores itself (SRAM), charge on a capacitor or trapped in an insulator (DRAM, flash), the magnetization of tiny grains (hard disks, tape), and the shape of a surface read with light (optical discs). This chapter looks at what each one physically holds, and why it forgets. How these cells are organized into chips and drives belongs to the levels above: registers and memory arrays on the digital-logic level, and Hard disks, SSDs and RAID and Optical discs and tape on the device level.

SRAM: a bit that holds itself

The simplest memory keeps no charge in reserve at all. It's a loop of two inverters, each feeding the other: if the first outputs 1, the second outputs 0, which keeps the first at 1. The loop has two stable states and actively returns to them after any small disturbance. That's the latch of the latches and flip-flops chapter, here with NOR gates:

Pulse S and Q goes to 1; release it, and Q stays 1: the loop remembers. Pulse R to clear it. An SRAM cell is the same idea in its most compact form: two cross-coupled CMOS inverters plus two access transistors that connect the cell to the bit lines for reading and writing — six transistors in all.

Because the loop restores itself continuously, SRAM needs no refresh and reads without disturbing the value. But the restoring is powered: the moment the supply drops, so does the bit. And every one of those transistors leaks the subthreshold current described in the MOSFET chapter, all the time, which makes large SRAMs costly in standby power as well as in area. That's why SRAM is used for registers and caches, and main memory is made of something denser.

DRAM: a bucket of electrons

A DRAM cell is one transistor and one capacitor (1T1C). The capacitor holds charge for a 1 and none for a 0; the transistor connects it to a bit line when its row is selected. That's all — which is why DRAM is several times denser than SRAM.

How much charge? DRAM cell capacitances have long been quoted in the 10–30 fF range, and designers go to great lengths — cells shaped like tall, narrow cylinders — to keep it from shrinking with the cell. Assume the cell is charged to about 1 V:

e = 1.602176634e-19
for C in (10e-15, 20e-15, 30e-15):
    print(C * 1e15, "fF:", C * 1.0 / e, "electrons")
# 10 fF: 62,415   20 fF: 124,830   30 fF: 187,245 electrons

A DRAM bit is on the order of 10⁵ electrons. That's the amount the read has to detect.

Reading destroys the bit

The bit line is long and connects to thousands of cells, so its own capacitance is several times the cell's. Before a read, the bit line is precharged to half the supply voltage. When the row opens, the cell and the bit line share their charge, and the bit line's voltage moves up or down by only a little. Assume the bit line has five times the cell's capacitance:

Cs, Cb, V = 20e-15, 100e-15, 1.0
print((V / 2) * Cs / (Cs + Cb) * 1000, "mV")   # 83 mV

The signal is a swing of less than a tenth of a volt. A sense amplifier — once again a pair of cross-coupled inverters, the SRAM loop used as a comparator — amplifies that small difference into a full 0 or 1. But the cell's charge has been diluted into the bit line: the read has destroyed it. The sense amplifier therefore writes the value back into the cell before the row closes. Every DRAM read is a read followed by a rewrite.

Why DRAM must be refreshed

Even untouched, the cell's charge leaks away: through the access transistor's subthreshold current, through the junction where the capacitor meets the silicon, and through the capacitor's insulator. How small must that leak be to keep the bit for 64 ms? Allow the cell to lose half of the charge of a 20 fF, 1 V cell:

Q = 20e-15 * 1.0 / 2
print(Q / 0.064, "A")          # 1.6e-13 A: 0.16 pA

The total leakage must stay below about a sixth of a picoampere — roughly a million electrons per second. It's remarkable that this can be made to work at all, in billions of cells. It can't be made to last: so the memory controller refreshes every row periodically, by reading it (and therefore rewriting it).

The JEDEC standards fix the schedule. DDR4 guarantees retention for 64 ms at normal temperatures; the controller issues 8,192 refresh commands in that window, one every 64 ms / 8,192 = 7.8 µs, each refreshing a slice of the rows. DDR5 halves the window to 32 ms, with a refresh command every 3.9 µs. Leakage roughly doubles with every ten degrees or so of temperature, and both standards refresh twice as often above 85 °C. Tanenbaum says each bit must be refreshed "every few milliseconds"; the standard window is tens of milliseconds, and the gap matters, since refresh steals bandwidth from the processor.

Tiny cells packed close together have a security side effect. In 2014, researchers showed that opening and closing one DRAM row very rapidly disturbs the charge in neighbouring rows enough to flip bits before their next refresh. Rowhammer, as it was named, was quickly turned into working privilege-escalation exploits, and DRAM makers now ship mitigations that refresh the neighbours of heavily used rows.

Flash: charge behind an insulator

DRAM leaks because its charge sits in contact with conducting silicon. Flash memory isolates the charge completely, inside the gate of a MOSFET.

A flash cell is a MOSFET with an extra layer between the control gate and the channel: a storage layer, surrounded by insulator on all sides. It comes in two versions:

• a floating gate: a small conductor (doped polysilicon) completely wrapped in oxide — the original design;
• a charge trap: a layer of silicon nitride, an insulator full of defects that each hold an electron. Because the charge can't move within the layer, one defect in the surrounding oxide leaks only the charge near it. Most of today's 3D NAND uses charge traps.

Electrons stored in that layer are negative charge sitting between the gate and the channel. They cancel part of the gate's voltage, so the cell's threshold voltage rises. To read, the chip applies a reference voltage to the control gate and checks whether the transistor conducts: below the raised threshold it doesn't, so the cell holds charge. No charge is consumed; the read is not destructive.

To get electrons through an insulator that is supposed to hold them for years, NAND flash applies a high voltage — around 20 V, generated on the chip — between the control gate and the channel. The field becomes strong enough for electrons to tunnel through the thin tunnel oxide (Fowler–Nordheim tunnelling, the quantum effect of the last chapter). Erasing reverses the field and pulls them back out, for a whole block of cells at a time.

Tanenbaum describes programming by hot-carrier injection at 12 V: accelerating electrons along the channel until a few have enough energy to jump into the floating gate. That's how NOR flash, the kind used for firmware, programs. The NAND flash in SSDs and phones programs and erases by tunnelling.

Many bits per cell

The threshold voltage doesn't have to be just high or low. By adding charge in small, carefully verified steps, the chip can place it at one of several levels, and a cell with 2ⁿ distinguishable levels stores n bits:

Within the same voltage window, n bits need 2ⁿ − 1 gaps, so each extra bit roughly halves the margin between neighbouring levels. The same number of leaked electrons then shifts a cell by a larger fraction of a gap, so each step up costs retention, endurance and write speed, recovered by stronger error-correcting codes. The book describes multilevel cells as typically holding two bits; today's SSDs are mostly TLC and QLC.

Wear and retention

Each program/erase cycle pushes electrons through the tunnel oxide at high field and slowly damages it, creating defects that trap charge and let it leak. The book's figure of about 100,000 cycles is right for SLC; today's TLC and QLC NAND is rated for far fewer — thousands of cycles for TLC, and typically around a thousand or less for QLC — which is why wear leveling and spare capacity matter so much.

Retention is specified too: the JEDEC standard for client SSDs requires data to survive one year unpowered at 30 °C once the drive has used up its rated endurance, and three months at 40 °C for enterprise drives. A fresh drive keeps data much longer. It's still charge in an insulator, and it still leaks eventually.

To keep growing density after planar cells reached their limits in the mid-2010s — at the smallest sizes, each level came down to a small number of electrons — NAND went vertical: 3D NAND stacks cells in columns more than two hundred layers high, using bigger cells with more charge per level.

Magnetism: disks and tape

A hard disk stores bits as the direction of magnetization in a thin film of a cobalt-based alloy. The film is made of grains less than ten nanometres across; within each grain the atoms' magnetic moments are locked together, pointing one way or the other along an easy axis. A bit is a patch of a few to a few tens of grains magnetized the same way; the data is actually encoded in the transitions between patches.

A grain's magnetization is held by an energy barrier proportional to its volume (the product KuV of the material's anisotropy and the grain volume). If the barrier gets too small compared with kT, heat flips grains at random: that's the superparamagnetic limit. The usual rule of thumb for data to last ten years is KuV ≥ about 60 kT:

k = 1.380649e-23
print(60 * k * 300 / e, "eV")   # 1.55 eV

Shrinking grains for density shrinks that barrier, which forces materials with higher anisotropy — and those are harder to write. Disk makers have gone through three answers:

• Perpendicular recording. Magnetize the grains up or down, into the disk, rather than along the track. The bits can be packed closer and the grains can be taller for the same area, raising V. Tanenbaum describes it as "likely to become the dominant technology"; it did, and every hard disk has used it since the late 2000s.
• Shingled recording overlaps tracks like roof tiles, since the read head is narrower than the write head.
• Heat-assisted recording (HAMR) heats each spot with a laser for a nanosecond while writing, lowering the barrier just long enough to flip it. Seagate began shipping HAMR drives of 30 TB and more in 2024.

The book's description of the head also needs updating. It says a coil in the head both writes and reads, the read relying on current induced as magnetized regions pass. Writing is still done with a coil. But since the 1990s disks have read with magnetoresistive sensors, whose electrical resistance depends on the direction of the field below: first giant magnetoresistance (whose discovery won Fert and Grünberg the 2007 Nobel Prize in physics), then tunnelling magnetoresistance, used in today's heads. The book also mentions "iron oxide": that was the coating of early disks and tapes, long replaced by metal-alloy thin films.

Light: pits and lands

An optical disc stores bits in the shape of a reflective surface. A pressed CD, DVD or Blu-ray has a spiral track of pits, read from below by a laser. The trick is interference: a pit's depth is about a quarter of the laser's wavelength inside the plastic, so light reflected from the bottom of a pit travels half a wavelength further than light from the surrounding land, and the two partly cancel. The detector sees less light over pits than over lands, and, as the book explains, a 1 is a transition between the two.

for lam in (780, 650, 405):          # CD, DVD, Blu-ray lasers, nm
    print(lam, lam / (4 * 1.55))     # quarter wave in polycarbonate (n ≈ 1.55)
# 780: 126 nm   650: 105 nm   405: 65 nm

The smallest spot a lens can focus is proportional to λ / NA, the wavelength divided by the lens's numerical aperture. Each optical generation shortened the wavelength and raised the NA:

The spot area shrinks with (λ/NA)²: 2.6 times from CD to DVD and 13 times from CD to Blu-ray. Capacity grew more than that — 6.7 and 36 times — thanks to tighter tolerances and more efficient error-correcting codes. The book lists 50 GB Blu-ray discs as "double-sided"; they're dual-layer, with two recording layers read from the same side.

Recordable discs replace pits with spots of dye darkened by a stronger laser. Rewritable ones use a phase-change alloy that can be switched between a crystalline and an amorphous state, with different reflectivities — the same physics used in phase-change memory chips, where the two states differ in electrical resistance instead.

Side by side

The same trade-off runs through the whole table. The easier a state is to change, the lower the barrier that holds it, and the sooner heat or leakage erases it. SRAM and DRAM change in nanoseconds and forget in milliseconds or at power-off; flash and disks take microseconds to milliseconds to write and keep data for years. The last chapter shows that erasing a bit always costs a minimum energy, set by the same kT.

Takeaways

• A stored bit is a physical state separated from the other by a barrier that must stay high compared with thermal energy kT — or be actively restored.
• SRAM is a loop of two inverters (6 transistors) that restores itself: fast, no refresh, but it forgets at power-off and leaks constantly.
• DRAM stores ~10⁵ electrons in a 10–30 fF capacitor. Reading shares that charge with a bit line (a swing of tens of millivolts), destroying it, so every read rewrites. Leakage must stay below ~0.16 pA, and rows are refreshed every 64 ms (DDR4) or 32 ms (DDR5).
• Flash traps charge in an insulated floating gate or charge-trap layer, shifting the transistor's threshold. NAND writes and erases by tunnelling at ~20 V. TLC and QLC store 3–4 bits as 8–16 levels, trading endurance and retention for density.
• Hard disks store bits in the magnetization of grains under 10 nm across, limited by thermal stability (KuV ≳ 60 kT). Perpendicular recording is universal, and heads read with magnetoresistive sensors, not coils.
• Optical discs use quarter-wave-deep pits; capacity follows (λ/NA)², from 780 nm (CD) to 405 nm (Blu-ray).