Level 5 / 9
Instruction set architecture
The contract between software and silicon: instruction formats, encodings, addressing modes.
L5 · Machine code
01 C8
Chapters
- 5.1Read →
What the ISA promises: memory model, alignment and ordering
- 5.2Read →
Instruction formats and encoding
- 5.3Read →
Addressing modes
- 5.4Read →
x86, ARM and RISC-V side by side
- 5.5Read →
Traps, interrupts and exceptions
- 5.6Read →
Data types the hardware understands
- 5.7Read →
VLIW, EPIC and the Itanium