Level 6 / 9
Microarchitecture
How one instruction becomes fetch, decode, execute: datapath, buses, caches and pipelines.
L6 · µops & buses
MAR ← rip · MEMR
Chapters
- 6.1Read →
The fetch–decode–execute cycle
- 6.2Read →
Datapath, internal and system buses
- 6.3Read →
Control units and microcode
- 6.4Read →
A complete machine: the Mic-1 running IJVM
- 6.5Read →
Pipelining and hazards
- 6.6Read →
Caches and the memory hierarchy
- 6.7Read →
Branch prediction
- 6.8Read →
Out-of-order execution, register renaming and speculation
- 6.9Read →
Real cores: x86, ARM and AVR compared
- 6.10Read →
SIMD, GPUs and coprocessors
- 6.11Read →
Multicore, multithreading and cache coherence
- 6.12Read →
Shared-memory multiprocessors and NUMA
- 6.13Read →
Clusters, message passing and supercomputers