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Computer Internals
Level 4 / 6

Microarchitecture

How one instruction becomes fetch, decode, execute: datapath, buses, caches and pipelines.

Try it in the simulator
MAR ← rip · MEMR

Chapters

  1. 4.1The fetch–decode–execute cyclePlanned
  2. 4.2Datapath, internal and system busesPlanned
  3. 4.3Control units and microcodePlanned
  4. 4.4Pipelining and hazardsPlanned
  5. 4.5Caches and the memory hierarchyPlanned
  6. 4.6Branch prediction and out-of-order executionPlanned
  7. 4.7Multicore and parallel machinesPlanned