Every circuit so far has been combinational: change the inputs and the outputs follow, with no memory of the past. But a computer is mostly memory — registers, caches, main memory — and even the pipeline needs to hold each instruction between stages. To remember a bit, a circuit needs one new ingredient: feedback, an output wired back into its own inputs.
The SR latch: two stable states
Cross-couple two NOR gates, each one's output feeding the other's input:
| S | R | Q | |
|---|---|---|---|
| 0 | 0 | Q | hold |
| 0 | 1 | 0 | reset |
| 1 | 0 | 1 | set |
| 1 | 1 | 0 | forbidden: Q = Q̄ = 0 |
Two cross-coupled NOR gates: the feedback loop stores one bit. S sets Q to 1, R resets it to 0, and with both at 0 the loop holds its value. To see why S = R = 1 is forbidden: turn auto off, set both to 1 and settle, then lower both before pressing step. Released in the same instant, the two gates race and oscillate forever.
Unit-delay model: every gate takes one step to react. With auto off, toggle switches and press step to watch the change travel gate by gate.
With both inputs at 0, the circuit has exactly two consistent states: Q = 0 (and Q̄ = 1), or Q = 1 (and Q̄ = 0). Each gate's output holds the other in place, so whichever state it's in, it stays there. That's one bit of memory.
- Raise S (set) briefly and Q becomes 1, and stays 1 after S goes back to 0.
- Raise R (reset) briefly and Q becomes 0, and stays 0.
- With S = R = 0, the latch holds whatever was set last.
S = R = 1 is forbidden. Both outputs are forced to 0, which is inconsistent with Q̄ being the inverse of Q. And when both inputs drop back to 0 at the same moment, the latch has no reason to prefer either state. With auto off, you can make exactly that happen: the simulator reports a race, the two gates chasing each other. In real hardware the latch eventually falls into one state at random.
The gated D latch
Two improvements make the latch usable. An enable input decides when it may change, and a single data input D replaces S and R, so the forbidden combination can't occur:
| E | D | Q | |
|---|---|---|---|
| 0 | x | Q | hold |
| 1 | 0 | 0 | transparent |
| 1 | 1 | 1 | transparent |
An SR latch (the two right NANDs, active-low) behind two gating NANDs. While E = 1 the latch is transparent and Q follows D; when E drops, Q keeps the last value. The inverter makes S and R always opposite, so the forbidden state cannot happen.
Unit-delay model: every gate takes one step to react. With auto off, toggle switches and press step to watch the change travel gate by gate.
While E = 1, the latch is transparent: Q follows D. When E drops to 0, Q keeps the last value D had. That's a true 1-bit memory, but only level-sensitive: for as long as E is high, any change on D goes straight through.
The clock
A computer coordinates millions of storage elements with a single signal: the clock, a square wave that alternates between 0 and 1 at a fixed rate. Its period is the length of one cycle: 250 ps at 4 GHz, 10 ns at 100 MHz. The clock usually starts as a quartz crystal oscillating at a few tens of MHz. On the chip, a phase-locked loop (PLL) multiplies that frequency up to the GHz range, and a distribution tree carries it to every corner of the chip with nearly the same timing.
Something must actually oscillate. Connect an odd number of inverting gates in a loop, and there is no stable state at all:
| EN | OUT |
|---|---|
| 0 | stable |
| 1 | oscillates, period 6 delays |
An odd number of inverting gates in a loop has no stable state. With EN = 1 the signal chases its own tail and the output toggles every 3 gate delays: the simulator detects the repeating state instead of settling. Real chips use this to measure gate speed.
Unit-delay model: every gate takes one step to react. With auto off, toggle switches and press step to watch the change travel gate by gate.
Turn EN on. The signal chases its own tail around the loop, and the output toggles every 3 gate delays, a period of 6. This is a ring oscillator. Real chips use them inside PLLs, and to measure how fast their own transistors are. The same effect is a bug when it happens by accident: any feedback loop with no stable state oscillates.
Why a latch isn't enough
Consider a register whose output goes through an adder and back into the same register, as in add eax, 1. If the register were a transparent latch, then while the enable is high, the new value would race around the loop: back through the adder, back into the latch, again and again, as long as the enable stays high. The result would depend on how long the pulse lasted.
The fix is to capture the input at an instant rather than during an interval.
The edge-triggered D flip-flop
A flip-flop samples D only at a clock edge, typically the rising one, and ignores D at all other times. The classic design is two D latches in series with opposite enables, a master and a slave:
| CLK | D | Q | |
|---|---|---|---|
| ↑ | 0 | 0 | rising edge: capture D |
| ↑ | 1 | 1 | rising edge: capture D |
| 0 | x | Q | hold (master follows D) |
| 1 | x | Q | hold (master closed) |
Two D latches in series with opposite enables. While CLK = 0 the master follows D and the slave holds; when CLK rises the master closes and the slave copies it. Q therefore changes only on the rising edge: this is the storage cell of registers and of every pipeline stage.
Unit-delay model: every gate takes one step to react. With auto off, toggle switches and press step to watch the change travel gate by gate.
While CLK = 0, the master follows D and the slave holds its value. When CLK rises, the master closes, freezing the value D had at that instant, and the slave opens and copies it to Q. While CLK = 1, D can change freely: the master is closed, so nothing gets through. Q changes only at the rising edge. Tanenbaum's text also shows another way to get the same behavior: a small pulse generator that turns each rising edge into a very short enable pulse for an ordinary latch.
The words are often mixed up, so to be precise: a latch is level-triggered (transparent while enabled), and a flip-flop is edge-triggered. In schematics, a small triangle on the clock input marks an edge-triggered flip-flop.
Timing rules
Every flip-flop has three timing numbers:
- setup time: D must be stable for a short time before the clock edge;
- hold time: D must stay stable for a short time after the edge;
- clock-to-Q delay: how long after the edge the new value appears on Q.
Between two flip-flops sits combinational logic — an adder, a mux, a comparator. The clock period must leave room for all of it:
period ≥ clock-to-Q + slowest path through the logic + setup time
This is the rule behind two earlier chapters. The slowest path through the datapath sets the clock speed, and pipelining raises the clock by inserting flip-flops — pipeline registers — to cut long paths into short ones. It's also why the ripple-carry adder is too slow: its path is longer than a cycle.
Break the setup or hold rule and the flip-flop can become metastable: its output hovers between 0 and 1 for an unpredictable time before settling. It happens with signals that come from outside the clock's control — a button, another chip, another clock domain. Designs pass such signals through two flip-flops in a row, a synchronizer, so that any metastability has a full cycle to resolve before the rest of the circuit sees the value.
From flip-flops to registers
Put n D flip-flops side by side, sharing one clock, and you have an n-bit register: it captures an n-bit value on every rising edge. Add a multiplexer in front of each D input that chooses between "the new value" and "my current value", and the register only updates when a load signal is set. Every register in the register file, every pipeline register, and the program counter itself is built this way. The next chapter goes from registers to memory arrays.
Takeaways
- Feedback gives a circuit memory. The SR latch has two stable states, and S = R = 1 is forbidden.
- A D latch is transparent while enabled and holds when disabled: it's level-triggered.
- The clock is a square wave, generated from a crystal and multiplied by a PLL. An odd loop of inverters oscillates.
- A D flip-flop (master-slave) captures D only on a clock edge, which makes feedback through logic safe.
- The clock period must cover clock-to-Q + logic delay + setup. Violating setup or hold risks metastability.
- A register is n flip-flops sharing a clock.